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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Rev. 02 -- 21 November 2007 Product data sheet
1. General description
The TDA8595 is a complementary quad Bridge Tied Load (BTL) audio power amplifier made in BCDMOS technology. It contains four independent amplifiers in BTL configuration. Through the I2C-bus, diagnosis of temperature warning and clipping level is fully programmable and the information available via two diagnostic pins is selectable. The status of each amplifier (output offset, load or no load, short-circuit or speaker incorrectly connected) can be read separately.
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2. Features
2.1 General
I I I I I I I I I I I I Operates in legacy mode (non I2C-bus) and I2C-bus mode (3.3 V and 5 V compliant) Three hardware-programmable I2C-bus addresses Drive 4 or 2 loads Speaker fault detection Independent short-circuit protection per channel Loss of ground and open VP safe (with 150 m series impedance and a supply decoupling capacitor of 2200 F maximum) All outputs short-circuit proof to ground, supply voltage and across the load All pins short-circuit proof to ground Temperature-controlled gain reduction to prevent audio holes at high junction temperatures Low battery voltage detection Offset detection This part has been qualified in accordance with AEC-Q100
2.2 I2C-bus mode
I DC load detection: open-circuit, short-circuit and load present I AC load (tweeter) detection I During start-up, can detect which load is connected so the appropriate gain can be selected without audio pop I Independently selectable soft mute of front channels (channel 1 and channel 3) and rear channels (channel 2 and channel 4) I Programmable gain (26 dB and 16 dB) of front channels and rear channels I Fully programmable diagnostic levels can be set: N Programmable clip detection: 2 %, 5 % or 10 % N Programmable thermal pre-warning
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
I Selectable information on the DIAG and STB pins: N The STB pin can be programmed/multiplexed with second clip detection N Clip information of each channel can be directed separately to the DIAG pin or the STB pin N Independent enabling of thermal, clip or load fault detection (short across or to VP or to ground) on DIAG pin
3. Quick reference data
Table 1. Quick reference data Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol VP Iq Po Parameter supply voltage quiescent current output power Conditions RL = 4 no load VP = 14.4 V RL = 4 ; THD = 0.5 % RL = 4 ; THD = 10 % RL = 4 ; maximum power; Vi = 2 V (RMS) square wave RL = 2 ; maximum power; Vi = 2 V (RMS) square wave THD Vn(o) total harmonic distortion noise output voltage RL = 4 ; f = 1 kHz; Po = 1 W to 12 W filter 20 Hz to 22 kHz; RS = 1 k normal mode line driver mode 45 22 65 29 V V 18 23 37 20 25 40 W W W Min 8 Typ 14.4 270 Max 18 400 Unit V mA
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58
64
-
W
-
0.01
0.1
%
4. Ordering information
Table 2. Type number TDA8595J TDA8595TH TDA8595SD Ordering information Package Name DBS27P HSOP36 RDBS27P Description plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm) plastic, heatsink small outline package; 36 leads; low stand-off height plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads (row spacing 2.54 mm) Version SOT827-1 SOT851-2 SOT878-1
TDA8595_2
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Product data sheet
Rev. 02 -- 21 November 2007
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
5. Block diagram
ADSEL SDA SCL VP1 21 (20, 21) VP2 7 (34, 35) 5 (33) STB 2 (29) STANDBY/ FAST MUTE I2C-BUS INTERFACE DIAG CLIP DETECT/DIAGNOSTIC
1 (28) 26 (26) 23 (22)
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12 (6)
MUTE
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
10 (4) 8 (2)
OUT1+ OUT1-
IN3
16 (12)
MUTE
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
18 (14) 20 (17)
OUT3+ OUT3-
IN2
13 (7)
MUTE
6 (30)
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
OUT2+ OUT2-
4 (32)
IN4
15 (11) VP
MUTE
22 (25)
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
OUT4+ OUT4-
24 (23)
TDA8595J TDA8595SD (TDA8595TH)
27 (36)
TAB
11 (5) SVR
14 (9) SGND
17 (13) ACGND
9 (3) PGND1
3 (31) PGND2
19 (16) PGND3
25 (24)
001aad135
PGND4
The pin numbers in parenthesis represent TDA8595TH.
Fig 1. Block diagram
TDA8595_2
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Product data sheet
Rev. 02 -- 21 November 2007
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
6. Pinning information
6.1 Pinning
ADSEL STB PGND2 OUT2- DIAG OUT2+
1 2 3 4 5 6 7 8 9
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VP2 OUT1- PGND1
OUT1+ 10 SVR 11 IN1 12 IN2 13 SGND 14 IN4 15 IN3 16 ACGND 17 OUT3+ 18 PGND3 19 OUT3- 20 VP1 21 OUT4+ 22 SCL 23 OUT4- 24 PGND4 25 SDA 26 TAB 27
001aad136
TDA8595J TDA8595SD
Fig 2. Pin configuration TDA8595J and TDA8595SD
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
TAB 36 VP2 35 VP2 34 DIAG 33 OUT2- 32 PGND2 31 OUT2+ 30 STB 29 ADSEL 28 n.c. 27 SDA 26 OUT4+ 25 PGND4 24 OUT4- 23 SCL 22 VP1 21 VP1 20 n.c. 19
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1 2 3 4 5 6 7 8
n.c. OUT1- PGND1 OUT1+ SVR IN1 IN2 n.c. SGND
TDA8595TH
9
10 n.c. 11 IN4 12 IN3 13 ACGND 14 OUT3+ 15 n.c. 16 PGND3 17 OUT3- 18 n.c.
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Fig 3. Pin configuration TDA8595TH
6.2 Pin description
Table 3. Symbol Pin description Pin TDA8595J TDA8595SD[1] ADSEL STB PGND2 OUT2- DIAG OUT2+ VP2 n.c. OUT1- PGND1 OUT1+ SVR IN1 IN2 n.c. SGND
TDA8595_2
Description TDA8595TH 28 29 31 32 33 30 34 and 35 1 2 3 4 5 6 7 8 9 I2C-bus address select standby (I2C-bus mode) or mode pin (legacy mode); programmable second clip indicator power ground channel 2 negative channel 2 output diagnostic/clip detection output positive channel 2 output supply voltage 2 not connected negative channel 1 output power ground channel 1 positive channel 1 output half supply filter capacitor channel 1 input channel 2 input not connected signal ground
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Pin description ...continued Pin TDA8595J TDA8595SD[1] TDA8595TH 10 11 12 13 14 15 16 17 18 and 19 20 and 21 25 22 23 24 26 27 36 not connected channel 4 input channel 3 input AC ground input positive channel 3 output not connected power ground channel 3 negative channel 3 output not connected supply voltage 1 positive channel 4 output I2C-bus clock input negative channel 4 output power ground channel 4 I2C-bus data input/output not connected heatsink connection; must be connected to ground Description
Table 3. Symbol
n.c. IN4 IN3 ACGND OUT3+ n.c. PGND3
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15 16 17 18 19 20 21 22 23 24 25 26 27
OUT3- n.c. VP1 OUT4+ SCL OUT4- PGND4 SDA n.c. TAB
[1]
To keep the output pins on the front side, special reverse bending is applied.
7. Functional description
The TDA8595 is a complementary quad BTL audio power amplifier made in BCDMOS technology. It contains four independent amplifiers in BTL configuration (see Figure 1). Through the I2C-bus, the diagnostic functions of temperature level and clip level are fully programmable and the information to be shown on the two diagnostic pins can be selected. The status of each amplifier (output offset, load or no load, short-circuit or speaker incorrectly connected) can be read separately. The TDA8595 is protected against overvoltage, short-circuit, over-temperature, open ground and open VP connections. Three different I2C-bus addresses are selected with an external resistor connected to the ADSEL pin. If the ADSEL pin is short-circuit to ground, the TDA8595 operates in legacy mode. In this mode, no I2C-bus is needed and the function of the STB pin will change from two level (Standby mode and On mode) to a three level pin (Standby mode, On mode and mute).
TDA8595_2
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Product data sheet
Rev. 02 -- 21 November 2007
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
7.1 Input stage
The input stage is a high-impedance pseudo-differential input stage. The negative inputs of the four channels are combined on the ACGND pin. For the best performance on supply voltage ripple rejection and pop noise, the capacitor connected to the ACGND pin must be four times the value of the input capacitor (or as close to the value as possible).
7.2 Output stage
The output stage of each amplifier channel consists of two PMOS power transistors and two NMOS transistors in BTL configuration. The process used is the BCDMOS process with an isolated substrate, SOI process, which has almost no parasitic components and therefore prevents latch-up.
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7.3 Distortion (clip-) detection
If the output of the amplifier starts clipping to the supply voltage or to ground, the output will become distorted. If the distortion per channel exceeds a selectable threshold (2 %, 5 % or 10 %), one of the two diagnostic pins (DIAG pin or STB pin) will be activated. To be able to detect if, for instance, the front channels (channel 1 and channel 3) or rear channels (channel 2 and channel 4) are clipping, the clip information can be directed per channel to the DIAG pin or the STB pin. It is possible to have only the clip information on the diagnostic pins by disabling the temperature and load information on the diagnostic pin. In this mode the temperature and load protection are still functional but can only be read via the I2C-bus.
7.4 Output protection and short-circuit operation
When a short-circuit to ground, VP or across the load occurs on one or more outputs of an amplifier, only the amplifier with the short-circuit is switched off. The channel that has a short-circuit and the type of short-circuit can be read-back via the I2C-bus. If the diagnostic pin is enabled for load fault information (IB2[D4] = 0) the DIAG pin will be pulled LOW. After 16 ms the amplifier will be switched on again and, if the short-circuit conditions still occur, the amplifier will be switched off. The 16 ms cycle will reduce the dissipation. To prevent audible distortion, the amplifier channel with the short-circuit can be disabled via the I2C-bus.
7.5 SOAR protection
The output transistors are protected by Safe Operating ARea (SOAR) protection. The TDA8595 has a two-stage SOAR protection:
* If the differential output voltage across the load is less than 1 V, and the current
through the load is more than 4 A, the amplifier channel will be switched off during 16 ms. To prevent incorrect switch-off with an inductive load or very high input signals, the condition (Vo < 1 V and IL > 4 A) must exist for more than 300 s.
* If the differential output voltage across the load is more than 1 V, and the current
through the load is more than 8 A, the amplifier channel will be switched off during 16 ms.
TDA8595_2
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Product data sheet
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I2C-bus controlled 4 x 45 W power amplifier
7.6 Speaker protection
To prevent damage of the speaker when one side of the speaker is connected to ground, a missing current protection is implemented. When in one channel the current in the high side power is not equal to the current in the low side power, a fault condition is assumed and the channel will be switched off. The speaker protection will be activated under the following conditions:
* Vo < 1.75 V and Imissing(det) > 1 A during 80 s * Vo > 1.75 V and Imissing(det) > 3 A during 80 s 7.7 Standby and mute operation
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The function of the STB pin is different in legacy mode and I2C-bus mode.
7.7.1 I2C-bus mode
When the STB pin is LOW, the total quiescent current is low, and the I2C-bus lines will not be loaded. When the STB pin is switched HIGH the TDA8595 is put in operating condition and will perform a power-on reset, which results in a LOW-level DIAG pin. The TDA8595 will start up when instruction bit IB1[D0] is set. Bit D0 will also reset the `power-on reset occurred' bit (DB2[D7]) and releases the DIAG pin. The soft mute and soft mute can be activated via the I2C-bus. The soft mute can be activated independently for the front channels (channel 1 and channel 3) and rear channels (channel 2 and channel 4), and mutes the audio in 20 ms. The fast mute activates the mute for all channels at the same time and mutes the audio in 0.1 ms. Releasing the mute after a fast mute will be by a soft un-mute of approximately 20 ms. When the STB pin is switched to Standby mode and the amplifier has started, first the fast mute will be activated and then the amplifier will shut-down. For instance, during an engine start, it is possible to fully mute the amplifiers within 100 s by switching the STB pin to zero.
7.7.2 Legacy mode (pin ADSEL connected to ground)
The function of the STB pin will change from standby/operating to standby/mute/operating and the amplifier will start directly when the STB is put into mute or operating. Mute operating is controlled via an internal timer (20 ms) to minimize mute-on pops. When the STB pin is switched directly from operating to standby, first the fast mute will be activated (switching to mute within 100 s) and then the amplifier will shut-down.
7.8 Start-up and shut-down sequence
To prevent the amplifier producing switch-on or switch-off pop noise, the capacitor on the SVR pin is used for smooth start-up and shut-down. Increasing the value of the SVR capacitor will mean a longer start-up and shut-down time. The amplifier output voltage is charged to half the supply voltage minus 1.4 V in mute condition, independent of the I2C-bus mute settings in I2C-bus mode or pin STB voltage in legacy mode. The last 1.4 V, where the output will reach half the supply voltage, is used to release the mute if the I2C-bus bits (IB2[D2:D0] = 000) were set to mute-off (VSTB > 6.5 V in legacy mode), or will stay in mute when the bits were set to mute (2.6 V < VSTB < 4.5 V in legacy mode).
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
When the amplifier is switched off by pulling the STB pin LOW, the amplifier is first muted (fast mute) and then the capacitor on the SVR pin is discharged. With an SVR capacitor of 22 F the standby current is reached 1 second after the STB pin is switched to zero (see Figure 4, Figure 5, Figure 6 and Figure 7). The start-up and shut-down pop can be further decreased by activating the low pop mode. When the low pop mode is enabled (IB2[D3] = 0), the output voltage rise from ground level during start-up will be slower (see Figure 6). This will decrease the pop even more but will increase the start-up time.
VP
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DIAG
DB2 bit D7 POR
IB1 bit D0 start enable twake
STB
SVR
tamp_on
toff fast mute
amplifier output
td(mute_off)
td(soft_mute)
td(fast_mute)
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Fig 4. Start-up and shut-down timing in I2C-bus mode
TDA8595_2
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Product data sheet
Rev. 02 -- 21 November 2007
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
VP
DIAG
DB2 bit D7 POR
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IB1 bit D0 start enable twake
STB
SVR tload tamp_on toff fast mute amplifier output
td(mute_off)
td(soft_mute)
td(fast_mute)
001aad169
Fig 5. Start-up and shut-down timing with DC load active in I2C-bus mode
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
VP
DIAG
DB2 bit D7 POR
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IB1 bit D0 start enable twake
STB
SVR tload tamp_on toff fast mute amplifier output
td(mute_off)
td(soft_mute)
td(fast_mute)
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Fig 6. Start-up and shut-down timing with low audible pop and DC load activated
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
VP
DIAG
on STB mute standby
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SVR
tamp_on soft mute amplifier output
toff fast mute
td(mute_off)
td(soft_mute)
td(mute_on)
td(fast_mute)
001aad171
Fig 7. Start-up and shut-down timing in legacy mode
7.9 Power-on reset and supply voltage spikes
If in I2C-bus mode the supply voltage drops below 5 V (see Figure 10) the content of the I2C-bus latches cannot be guaranteed and the power-on reset will be activated. All latches are reset, the amplifier is switched off and the DIAG pin is pulled LOW to indicate that a power-on reset has occurred (see bit DB2[D7]). When bit IB1[D0] is set, the power-on flag is reset, the DIAG pin will be released and the amplifier will start-up. In legacy mode a supply voltage drop below 5 V will switch off the amplifier and the DIAG pin will not be pulled LOW.
7.10 Engine start and low voltage operation
The DC output voltage of the amplifier (VO) is set to half of the supply voltage and is related to the voltage on the SVR pin (see Figure 8; VO = VSVR - 1.4 V). A capacitor is connected on the SVR pin to suppress the ripple on the power supply. If the supply voltage drops, for instance, during an engine start, the output follows slowly due to the SVR capacitor. The headroom voltage is the voltage needed for good operation of the amplifier and is defined as Vhr = VP - VO (see Figure 8). If the headroom voltage becomes lower than the headroom protection threshold of 1.6 V, the headroom protection is activated to prevent pop noise at the output. This protection first activates the hard mute and then discharges the capacitors on the SVR and ACGND pins to generate more headroom for the amplifier (see Figure 9.)
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
When the SVR capacitor has discharged, the amplifier starts up again if the VP voltage is above the low VP mute threshold, typically 7.5 V. Below the low VP mute threshold, the outputs of the amplifier remain low. In I2C-bus mode, a supply voltage drop below VP(reset), typically 5 V, results in setting bit DB2[D7]. The amplifiers will not start-up but wait for an I2C-bus command to start-up. The amplifier prevents audio pops during engine start. To prevent pops on the output caused by the application during an engine start (for instance tuner regulator out of regulation), the STB pin can be made zero when an engine start is detected. The STB pin activates the fast mute and disturbances at the amplifier inputs are suppressed.
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V (V)
14
VP
VSVR 8.4 7 VO (2) headroom protection threshold (3) Vhr (1)
1.6 V
t (s)
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(1) Headroom voltage Vhr = VP - VO. (2) Steady state output voltage VO = VSVR - 1.4 V. (3) Headroom protection threshold = VO + 1.6 V.
Fig 8. Low headroom protection
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
VO (V) 14.4
legacy and I2C-bus mode VP output voltage
8.8 8.6 7.2
(1)
Vhr
(2) (3)
VSVR
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output voltage
(3)
t(start-Vo(off)) t(start-SVRoff)
t (s)
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(1) Headroom protection activated: a) Fast mute b) Discharge of SVR. (2) Low VP mute activated. (3) Low VP mute released.
Fig 9. Low VP behavior; legacy and I2C-bus modes
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
VO (V) 14.4
I2C-bus mode only VP
8.8 8.6
(1)
7.2
(2)
5.0 3.5 www..com VSVR output voltage 0 POR IB1 bit D0
DIAG
t (s)
001aad185
(1) Low VP mute activated. (2) VPOR: VP level at which Power-On Reset (POR) is activated.
Fig 10. Low VP behavior; I2C-bus mode only
7.11 Overvoltage and load dump protection
When the battery voltage VP is higher than 22 V, the amplifier stage will be switched to high-impedance. The TDA8595 is protected against load dump voltage with supply voltage up to 50 V.
7.12 Thermal pre-warning and thermal protection
If the average junction temperature reaches a level that is adjustable via the I2C-bus, selected with bit IB3[D4], the pre-warning will be activated resulting in a LOW-level on pin DIAG (if selected) and can be read out via the I2C-bus. The default setting for the thermal pre-warning is IB3[D4] = 0, setting the warning level at 145 C. In legacy mode the thermal pre-warning is set at 145 C. If the temperature increases further, the temperature controlled gain reduction will be activated for all four channels to reduce the output power (see Figure 11). If this does not reduce the average junction temperature, all four channels will be switched off at the absolute maximum temperature Toff, typical 175 C.
TDA8595_2
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Product data sheet
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I2C-bus controlled 4 x 45 W power amplifier
30 Gv (dB) 20
001aad174
10
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0 145
155
165 Tj (C)
175
Fig 11. Temperature controlled amplifier gain
7.13 Diagnostics
Diagnostic information can be read via the I2C-bus, and can also be available on the DIAG pin or on the STB pin. The DIAG pin has both fixed information (power-on reset occurred, low battery and high battery) and, via the I2C-bus, selectable information (temperature, load fault and clip). This information will be seen at the DIAG pin as a logic OR. In case of a failure, the DIAG pin remains LOW and the microprocessor can read the failure information via the I2C-bus (the DIAG pin can be used as microprocessor interrupt to minimize I2C-bus traffic). When the failure is removed, the DIAG pin will be released. To have full control over the clipping information, the STB pin can be programmed as a second clip detection pin. The clip detection level can be selected for all channels at once. It is possible to select whether the clip information is available on the DIAG pin or on the STB pin, for each channel separately. It is, for instance, possible to distinguish between clipping of the front and the rear channels. Diagnostic information selection possibilities are shown in Table 4.
Table 4. Diagnostic information availability I2C-bus mode DIAG pin STB pin no after power-on reset, DIAG pin will remain LOW until amplifier has been started yes can be enabled per channel can be enabled can be enabled no can be enabled per channel no no Legacy mode DIAG pin no
Diagnostic information Power-On Reset (POR)
Low battery Clip detection Temperature prewarning Short
yes yes, fixed level for all channels on 2 % yes, pre-warning level is 145 C yes
TDA8595_2
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Product data sheet
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I2C-bus controlled 4 x 45 W power amplifier
Diagnostic information availability ...continued I2C-bus mode DIAG pin can be enabled no no yes STB pin no no no no Legacy mode DIAG pin yes no no yes
Table 4.
Diagnostic information Speaker protection (missing current) Offset detection Load detection Overvoltage
7.14 Offset detection
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The offset detection can be performed with no input signal (for instance when the DSP is in mute after a start-up) or with an input signal. In I2C-bus mode, if an I2C-bus read of the output offset is performed, the I2C-bus latches DBx[D2] will be set. When the amplifier BTL output voltage is within a window with threshold of 1.75 V typical, the latches DBx[D2] are reset and setting is disabled. If, for instance, after one second an I2C-bus read is performed again and the offset bits are still set, the output has not crossed the offset threshold during the last second (see Figure 12). This can mean the applied frequency is below 1 Hz (one second I2C-bus read interval) or an output offset of more than 1.75 V is present.
I2C-bus mode only
VO = VOUT+ - VOUT-
offset threshold reset: setting disabled
t
t = 1 s: read = no offset DB1 bit D2 reset
VO = VOUT+ - VOUT-
offset threshold read = set bit t = 1 s: read = offset DB1 bit D2 set
t
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Fig 12. Offset detection
7.15 DC load detection
When the DC load detection is enabled with bit IB1[D1], an offset is slowly applied at the output of the amplifiers during the start-up cycle and the load currents are measured. Different load levels will be detected to differentiate between normal load, line driver load or open load (see Figure 13).
TDA8595_2
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Product data sheet
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I2C-bus controlled 4 x 45 W power amplifier
LOAD DETECTION LEVEL
NORMAL 20
LINE DRIVER MODE 100 800
OPEN-CIRCUIT
5 k
001aad176
Fig 13. DC load detection levels
If the amplifier is used as line driver and the external booster has an input impedance of more than 100 and less than 800 (DC-coupled), the DC load bits will contain DBx[D5:D4] = 10, independent of the gain setting (see Table 5).
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Table 5. DBx[D5] 0 1 1 0
DC load detection Meaning (when IB1[D2] = 0) DBx[D4] 0 0 1 1 normal load line driver load open load not valid
DC load bits
By reading the I2C-bus bits the microprocessor can determine, after the start-up of the amplifier, whether a speaker or an external booster is connected. Depending on these bits, the amplifier gain can be selected, 26 dB for normal mode or 16 dB for line driver mode. If the gain select is performed when the amplifier is muted, the gain select will be pop free. The DC load bits are combined with the AC load bits and are only valid when the AC load detection is disabled. When the AC load detection is enabled (IB1[D2] = 1), the bits DBx[D4] will show the content of the AC load detection. When the AC load detection is disabled again, bit DBx[D4] will show the content of the DC load measurement, which was stored during the AC load measurement. The AC load detection can only be performed after the amplifier has completed its start-up cycle and will not conflict with the DC load detection.
7.16 AC load detection
The AC load detection, enabled with IB1[D2] = 1, is used to detect if AC coupled speakers, for example tweeters, are connected correctly during assembly. The detection is audible because a sine wave of a certain frequency (e.g. 19 kHz) needs to be applied to the inputs of the amplifier. The output voltage over the load impedance will generate an amplifier current. If the amplifier peak current triggers a 460 mA (peak) threshold detector three times, the AC load detection bit will be set. A three `threshold cross' counter is used to prevent false AC load detection when switching the input signal on or off. An AC coupled speaker will reduce the impedance at the output of the amplifier in a certain frequency band. The presence of an AC coupled speaker can be determined using 460 mA (peak) and 230 mA (peak) threshold current detection. For instance, at an output voltage of 2 V (peak) the total impedance must be less than 4 to detect the AC coupled load, or more than 8 to guarantee only a DC connection is detected.
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
The interpretation of line driver and normal mode DC load bit setting for AC load detection is shown in Table 6.
Table 6. DBx[D4] 0 1 AC load detection Meaning (when IB1[D2] = 1) no AC load detected AC load detected
When bit IB1[D2] = 1, the AC load detection is enabled. The AC load detection can only be performed after the amplifier has completed its start-up cycle and will not conflict with the DC load detection.
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20 |Zth(load)| () 16
001aad177
(1)
12
8
(2)
4
0 0 1 2 3 4 VoM (V) 5
(1) IoM < 230 mA (no load detection level) (2) IoM > 460 mA (load detection level)
Fig 14. AC load impedance as a function of peak output voltage
7.17 I2C-bus diagnostic readout
The diagnostic information of the amplifier can be read via the I2C-bus. The I2C-bus bits are set on a failure and will be reset with the I2C-bus read command. Even when the failure is removed, the microprocessor will know what was wrong by reading the I2C-bus. The consequence of this procedure is that old information is read during the I2C-bus readout. Most actual information will be gathered after two successive read commands. The DIAG pin will give actual diagnostic information (when selected). When a failure is removed, the DIAG pin will be released instantly, independently of the I2C-bus latches.
TDA8595_2
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
8. I2C-bus specification
Table 7. Open 51 k to ground 10 k to ground Ground TDA8595 hardware address select A6 1 1 1 no A5 1 1 1 I2C-bus; A4 0 0 0 A3 1 1 1 A2 1 1 1 A1 0 0 1 A0 0 1 1 R/W 0 = write to TDA8595 1 = read from TDA8595 0 = write to TDA8595 1 = read from TDA8595 0 = write to TDA8595 1 = read from TDA8595
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Pin ADSEL
legacy mode
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 15. Definition of START and STOP conditions
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 16. Bit transfer
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
I2C-BUS WRITE SCL 1 2 7 8 9 1 2 7 8 9
SDA
MSB
MSB - 1
LSB + 1
ACK
MSB
MSB - 1
LSB + 1
LSB
ACK
S
ADDRESS
W
A
WRITE DATA
A
P
To stop the transfer, after the last acknowledge (A) a STOP condition (P) must be generated I2C-BUS READ
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SCL
1
2
7
8
9
1
2
7
8
9
SDA
MSB
MSB - 1
LSB + 1
ACK
MSB
MSB - 1
LSB + 1
LSB
ACK
S
ADDRESS
R
A
READ DATA
NA
P
: generated by master (microcontroller) : generated by slave S P A NA R/W : START : STOP : acknowledge : not acknowledge : read / write
To stop the transfer, the last byte must not be acknowledged and a STOP condition (P) must be generated
001aac649
Fig 17. I2C-bus read and write modes
8.1 Instruction bytes
I2C-bus mode:
* If R/W bit = 0, the TDA8595 expects three instruction bytes; IB1, IB2 and IB3 * After a power-on reset, all instruction bits are set to zero
Legacy mode:
* All bits equal to zero define the setting, with the exception of bit IB1[D0] which is
ignored (see Table 8).
Table 8. Bit D7 D6 Instruction byte IB1 Description don't care channel 3 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin D5 channel 1 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Instruction byte IB1 ...continued Description channel 4 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin
Table 8. Bit D4
D3
channel 2 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin
D2
AC load detection enable: 0 = AC load detection disabled 1 = AC load detection enabled; bit DBx[D4] not available for DC load detection
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D1
DC load detection enable: 0 = DC load detection disabled 1 = DC load detection enabled
D0
amplifier start enable 0 = amplifier not enabled, DIAG pin will remain LOW 1 = amplifier will start up, power-on occurred (DB2[D7] will be reset) and DIAG pin will be released
Table 9. Bit D7 and D6
Instruction byte IB2 Description clip detection level 00 = clip detection level 2 % 01 = clip detection level 5 % 10 = clip detection level 10 % 11 = clip detection level disabled
D5
temperature information on DIAG pin 0 = temperature information on DIAG pin 1 = no temperature information on DIAG pin
D4
load fault information (shorts, missing current) on DIAG pin 0 = fault information on DIAG pin 1 = no fault information on DIAG pin
D3
low pop (slow start) enable 0 = low pop enabled 1 = low pop disabled
D2
soft mute channel 1 and channel 3 (mute delay 20 ms) 0 = no mute 1 = mute
D1
soft mute channel 2 and channel 4 (mute delay 20 ms) 0 = no mute 1 = mute
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Instruction byte IB2 ...continued Description fast mute all amplifier channels (mute delay 100 s) 0 = no mute 1 = mute
Table 9. Bit D0
Table 10. Bit D7 D6
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Instruction byte IB3 Description don't care amplifier channel 1 and channel 3 gain select 0 = 26 dB 1 = 16 dB
D5
amplifier channel 2 and channel 4 gain select 0 = 26 dB 1 = 16 dB
D4
temperature pre-warning level 0 = warning level on 145 C 1 = warning level on 122 C
D3
disable channel 3 0 = channel 3 enabled 1 = channel 3 disabled
D2
disable channel 1 0 = channel 1 enabled 1 = channel 1 disabled
D1
disable channel 4 0 = channel 4 enabled 1 = channel 4 disabled
D0
disable channel 2 0 = channel 2 enabled 1 = channel 2 disabled
8.2 Data bytes
I2C-bus mode:
* If R/W = 1, the TDA8595 sends four data bytes to the microprocessor: DB1, DB2,
DB3 and DB4
* All bits except DB1[D7] and DB3[D7] are latched * All bits except DBx[D4] and DBx[D5] are reset after a read operation. Bit DBx[D2] is
set after a read operation, see Section 7.14
* For explanation of AC and DC load detection bits, see Section 7.15 and Section 7.16
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Data byte DB1 Description temperature pre-warning 0 = no warning 1 = junction temperature too high
Table 11. Bit D7
D6
speaker fault channel 2 (missing current) 0 = no missing current 1 = missing current
D5 and D4
channel 2 DC load or AC load detection if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don't care, bit D4 has the following meaning
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0 = no AC load 1 = AC load detected if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid 10 = line driver load 11 = open load D3 channel 2 shorted load 0 = not shorted load 1 = shorted load D2 channel 2 output offset 0 = no output offset 1 = output offset D1 channel 2 short to VP 0 = no short to VP 1 = short to VP D0 channel 2 short to ground 0 = no short to ground 1 = short to ground Table 12. Bit D7 Data byte DB2 Description power-on reset and amplifier status 0 = amplifier on 1 = power-on reset has occurred; amplifier off D6 speaker fault channel 4 (missing current) 0 = no missing current 1 = missing current
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Data byte DB2 ...continued Description channel 4 DC load or AC load detection if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don't care, bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid
Table 12. Bit D5 and D4
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10 = line driver load 11 = open load D3 channel 4 shorted load 0 = not shorted load 1 = shorted load D2 channel 4 output offset 0 = no output offset 1 = output offset D1 channel 4 short to VP 0 = no short to VP 1 = short to VP D0 channel 4 short to ground 0 = no short to ground 1 = short to ground Table 13. Bit D7 Data byte DB3 Description maximum temperature protection 0 = no protection 1 = maximum temperature protection D6 speaker fault channel 1 (missing current) 0 = no missing current 1 = missing current
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Data byte DB3 ...continued Description channel 1 DC load or AC load detection if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don't care, bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid
Table 13. Bit D5 and D4
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10 = line driver load 11 = open load D3 channel 1 shorted load 0 = not shorted load 1 = shorted load D2 channel 1 output offset 0 = no output offset 1 = output offset D1 channel 1 short to VP 0 = no short to VP 1 = short to VP D0 channel 1 short to ground 0 = no short to ground 1 = short to ground Table 14. Bit D7 D6 Data byte DB4 Description reserved speaker fault channel 3 (missing current) 0 = no missing current 1 = missing current D5 and D4 channel 3 DC load or AC load detection if bit IB1[D2] = 1, AC load detection is enabled, bit D5 is don't care, bit D4 has the following meaning 0 = no AC load 1 = AC load detected if bit IB1[D2] = 0, AC load detection is disabled, bits D5 and D4 are available for DC load detection 00 = normal load 01 = not valid 10 = line driver load 11 = open load
TDA8595_2
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Data byte DB4 ...continued Description channel 3 shorted load 0 = not shorted load 1 = shorted load
Table 14. Bit D3
D2
channel 3 output offset 0 = no output offset 1 = output offset
D1
channel 3 short to VP 0 = no short to VP 1 = short to VP
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D0
channel 3 short to ground 0 = no short to ground 1 = short to ground
9. Limiting values
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Parameter supply voltage Conditions operating non operating load dump protection; duration 50 ms, rise time > 2.5 ms VP(r) IOSM IORM Tj(max) Tstg Tamb V(prot) reverse supply voltage non-repetitive peak output current repetitive peak output current maximum junction temperature storage temperature ambient temperature protection voltage AC and DC short-circuit voltage of output pins and across the load 10 minutes maximum Min -1 Max 18 +50 50 Unit V V V
-55 -40 -
-2 13 8 150 +150 +105 VP
V A A C C C V
Vx
voltage on pin x SCL and SDA IN1, IN2, IN3, IN4, SVR, ACGND and DIAG STB 0 0 6.5 13 V V
0
24
V
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Table 15. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Ptot Vesd Parameter total power dissipation electrostatic discharge voltage Conditions Tcase = 70 C human body model; C = 100 pF; Rs = 1.5 k machine model; C = 200 pF; Rs = 10 ; Ls = 0.75 H Min Max 80 2000 200 Unit W V V
10. Thermal characteristics
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Table 16. Symbol Rth(j-c) Rth(j-a) Rth(j-c) Rth(j-a)
Thermal characteristics Parameter thermal resistance from junction to case thermal resistance from junction to ambient in free air thermal resistance from junction to case thermal resistance from junction to ambient in free air Conditions Typ 1 40 1 40 Unit K/W K/W K/W K/W
TDA8595J; TDA8595SD
TDA8595TH
11. Characteristics
Table 17. Characteristics Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol VP Iq Istb VO VP(low)(mute) VP(low)(mute) Vth(ovp) Vhr VPOR VO(offset) Parameter supply voltage quiescent current standby current output voltage low supply voltage mute low supply voltage mute hysteresis overvoltage protection threshold voltage headroom voltage power-on reset voltage output offset voltage when headroom protection is activated; see Figure 8 see Figure 9 amplifier on amplifier mute line driver mode
TDA8595_2
Conditions RL = 4 RL = 2 no load VSTB = 0.4 V with rising supply voltage with falling supply voltage
[1]
Min 8 8 6.7 6.9 6.3 0.1 18 1.1 4.1 -95 -25 -40
Typ 14.4 14.4 270 4 7 7.5 6.8 0.7 20 1.6 5.0 0 0 0
Max 18 16 400 15 7.2 8 7.4 1 22 2.0 5.8 +95 +25 +40
Unit V V mA A V V V V V V V mV mV mV
Supply voltage behavior
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Table 17. Characteristics ...continued Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol RL(tol) Parameter load resistance tolerance Conditions VP 18 V VP 16 V Mode select and second clip detection: pin STB VSTB voltage on pin STB Standby mode selected I2C-bus mode legacy mode mute selected
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Min 3.2 1.6
Typ 4 2
Max -
Unit
2.5 2.5 6.5
[2]
-
1 1 4.5 VP VP
V V V V V
legacy mode Operating mode selected I2C-bus mode legacy mode low voltage on pin STB when pulled down during clipping ISTB = 150 A ISTB = 500 A
5.6 6.1 -
4 10 300
6.1 7.2 30 70 500
V V A A s
ISTB
current on pin STB
VSTB from 0 V to 8.5 V clip detection not active; I2C-bus mode legacy mode
Start-up / shut-down / mute timing twake wake-up time time after wake-up via STB pin before first I2C-bus transmission is recognized; see Figure 4
ILO(SVR) td(mute_off)
output leakage current on pin SVR mute off delay time 10 % of output signal; ILO = 0 A I2C-bus mode; with ILO = 10 A +15 ms; no DC load (IB1[D1] = 0); low pop disabled (IB2[D3] = 1); see Figure 4 I2C-bus mode; with ILO = 10 A +20 ms; DC load active (IB1[D1] = 1); low pop disabled (IB2[D3] = 1); see Figure 5 I2C-bus mode; with ILO = 10 A +20 ms; DC load active (IB1[D1] = 1); low pop enabled (IB2[D3] = 0); see Figure 6 legacy mode; with ILO = 10 A +20 ms; VSTB = 7 V; RADSEL = 0 ; see Figure 7
[3]
-
-
10
A
295
465
795
ms
500
640
940
ms
640
830
1190
ms
430
650
1030
ms
TDA8595_2
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Table 17. Characteristics ...continued Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol tamp_on Parameter amplifier on time Conditions time from amplifier mute to amplifier on; 90 % of output signal; ILO = 0 A I2C-bus mode; with ILO = 10 A +30 ms; no DC load (IB1[D1] = 0); low pop disabled (IB2[D3] = 1); see Figure 4
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[3]
Min
Typ
Max
Unit
360
520
870
ms
I2C-bus mode; with ILO = 10 A +35 ms; DC load active (IB1[D1] = 1); low pop disabled (IB2[D3] = 1); see Figure 5 I2C-bus mode; with ILO = 10 A +30 ms; DC load active (IB1[D1] = 1); low pop enabled (IB2[D3] = 0); see Figure 6 legacy mode; with ILO = 10 A +20 ms; VSTB = 7 V; RADSEL = 0 ; see Figure 7
565
695
1015
ms
710
890
1270
ms
510
720
1120
ms
toff
amplifier switch-off time
time to DC output voltage < 0.1 V; I2C-bus mode; ILO = 0 A low pop disabled (IB2[D3] = 1); with ILO = 10 A +0 ms; see Figure 5 low pop enabled (IB2[D3] = 0); with ILO = 10 A +0 ms; see Figure 6
[3]
120
245
530
ms
140
280
620
ms
td(mute-on)
mute to on delay time
from 10 % to 90 % of output signal; IB2[D1/D2] = 1 to 0; Vi = 50 mV; see Figure 7 from 90 % to 10 % of output signal; Vi = 50 mV; IB2[D1/D2] = 0 to 1; see Figure 7 from 90 % to 10 % of output signal; VSTB from 8 V to 1.3 V; see Figure 7 VP from 14.4 V to 7 V; Vo < 0.5 V; see Figure 9 VP from 14.4 V to 7 V; VSVR < 2 V; see Figure 9 pins SCL and SDA pins SCL and SDA pin SDA; IL = 5 mA
-
20
40
ms
td(soft_mute)
soft mute delay time
-
20
40
ms
td(fast_mute)
fast mute delay time
-
0.1
1
ms
t(start-Vo(off)) t(start-SVRoff)
engine start to output off time engine start to SVR off time LOW-level input voltage HIGH-level input voltage LOW-level output voltage
-
0.1 40
1 75
ms ms
I2C-bus interface[4] VIL VIH VOL
TDA8595_2
2.3 -
-
1.5 5.5 0.4
V V V
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Table 17. Characteristics ...continued Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol fSCL RADSEL Parameter SCL clock frequency resistance on pin ADSEL address A[6:0] = 110 1100 I2C-bus address A[6:0] = 110 1101 I2C-bus address A[6:0] = 110 1111 legacy mode
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Conditions I2C-bus
Min 155 42 7 1.5
Typ 400 51 10 1.75 10 5 2 4 3.5 145 122 155
Max 57 15 0.5 0.3 2.2 16 7 3 9 6 155 132 160
Unit kHz k k k k V V % % % % % C C C
VOL(DIAG) VO(offset_det) THDclip
LOW-level output voltage on pin DIAG output voltage at offset detection total harmonic distortion clip detection level
fault condition; IDIAG = 1 mA
IB2[D7:D6] = 10 IB2[D7:D6] = 01 IB2[D7:D6] = 00
5 3 1 1 1 135 112 150
THDclip
total harmonic distortion between IB2[D7:D6] = 10 and clip detection level variation IB2[D7:D6] = 01 between IB2[D7:D6] = 01 and IB2[D7:D6] = 00
Tj(AV)(pwarn) Tj(AV)(G(-0.5dB))
pre-warning average junction temperature
IB3[D4] = 0 IB3[D4] = 1
average junction Vi = 0.05 V temperature for 0.5 dB gain reduction
Tj(pw-G(-0.5dB)) prewarning to 0.5 dB gain reduction junction temperature difference Tj(G(-0.5dB)-off) difference in junction temperature between 0.5 dB gain reduction and off G(th_fold) Zth(load) gain reduction of thermal foldback load detection threshold impedance all channels will switch off I2C-bus mode normal load detection line driver load detection Zth(open) Ith(o)det(load)AC open load detection threshold impedance AC load detection output threshold current I2C-bus mode
7
10
13
C
10
15
20
C
-
20
-
dB
100 5000
-
20 800 -

I2C-bus mode AC load bit is set AC load bit is not set 460 230 mA mA
TDA8595_2
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Table 17. Characteristics ...continued Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol Amplifier Po output power RL = 4 ; VP = 14.4 V; THD = 0.5 % RL = 4 ; VP = 14.4 V; THD = 10 % RL = 4 ; VP = 14.4 V; maximum power; Vi = 2 V (RMS) square wave
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Parameter
Conditions
Min 18 23 37
Typ 20 25 40
Max -
Unit W W W
RL = 4 ; VP = 15.2 V; maximum power; Vi = 2 V (RMS) square wave RL = 2 ; VP = 14.4 V; THD = 0.5 % RL = 2 ; VP = 14.4 V; THD = 10 % RL = 2 ; VP = 14.4 V; maximum power; Vi = 2 V (RMS) square wave
41
45
-
W
29 37 58
32 41 64
-
W W W
THD
total harmonic distortion
Po = 1 W to 12 W; f = 1 kHz; RL = 4 Po = 1 W to 12 W; f = 10 kHz Po = 1 W to 12 W; f = 20 kHz line driver mode; Vo = 1 V (RMS) and 5 V (RMS), f = 20 Hz to 20 kHz; complex load; see Figure 32
-
0.01 0.09 0.14 0.02
0.1 0.3 0.4 0.05
% % % %
cs
channel separation
f = 1 kHz; RS = 1 k; RACGND = 250 f = 10 kHz; RS = 1 k; RACGND = 250
[5]
65 60 55 45
80 65 70 65
-
dB dB dB dB
[5]
SVRR CMRR
supply voltage ripple rejection common mode rejection ratio maximum common mode voltage (RMS value) output noise voltage
100 Hz to 10 kHz; RS = 1 k; RACGND = 250 normal mode; Vcm = 0.3 V (p-p); f = 1 kHz to 3 kHz, RS = 1 k; RACGND = 250 f = 1 kHz filter 20 Hz to 22 kHz; RS = 1 k mute mode line driver mode normal mode
[5]
[5]
Vcm(max)(rms) Vn(o)
-
-
0.6
V
25.5 15.5
19 22 45 26 16
26 29 65 26.5 16.5
V V V dB dB
Gv
voltage gain
single ended in; differential out normal mode line driver mode
TDA8595_2
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Product data sheet
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Table 17. Characteristics ...continued Refer to test circuit (see Figure 30) at VP = VP1 = VP2 = 14.4 V; RL = 4 ; f = 1 kHz; RS = 0 ; normal mode; unless otherwise specified. Tested at Tamb = 25 C; guaranteed for Tamb = -40 C to +105 C. Symbol Zi mute Vo(mute)(RMS) Bp Parameter input impedance mute attenuation RMS mute output voltage power bandwidth Conditions Tamb = -40 C to +105 C Tamb = 0 C to 105 C Vo / Vo(mute); Vi = 50 mV Vi = 1 V (RMS); filter 20 Hz to 22 kHz -1 dB Min 50 60 80 Typ 70 70 92 25 20 to 20000 Max 95 95 Unit k k dB V Hz
[1] Operation above www..com 16 V in a 2 mode with reactive load can trigger the amplifier protection. The amplifier switches off and will restart after 16 ms resulting in an `audio hole'. [2] [3] VSTB depends on the current into the STB pin: minimum = (1429 x ISTB) + 5.4 V, maximum = (3143 x ISTB) + 5.6 V. The times are specified without leakage current. For a leakage current of 10 A on the SVR pin, the delta time is specified. If the capacitor value on the SVR pin changes with 30 %, the specified time will also change with 30 %. The specified times include an ESR of 15 for the capacitor on the SVR pin. Standard I2C-bus specification: maximum LOW-level = 0.3 x VDD, minimum HIGH-level = 0.7 x VDD. To comply with 5 V and 3.3 V logic the maximal LOW-level is defined by VDD = 5 V and the minimum HIGH-level by VDD = 3.3 V. For optimum channel separation (cs), supply voltage ripple rejection (SVRR) and common mode rejection ratio (CMRR), a resistor
[4] [5]
RS R ACGND = ----- should be in series with the ACGND capacitor. 4
12. Performance diagrams
102 THD (%) 10
001aad139
1
10-1
(1)
10-2
(2) (3)
10-3
10-2
10-1
1
10 Po (W)
102
VP = 14.4 V. (1) f = 10 kHz. (2) f = 1 kHz. (3) f = 100 Hz.
Fig 18. Total harmonic distortion as a function of output power; 4 load
TDA8595_2
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
102 THD (%) 10
001aad140
1
10-1
(1) (2)
10-2
(3)
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10-3 10-2 10-1
1
10 Po (W)
102
VP = 14.4 V. (1) f = 10 kHz. (2) f = 100 Hz. (3) f = 1 kHz.
Fig 19. Total harmonic distortion as a function of output power; 2 load
28 Po (W) 26
(1)
001aad141
24
22
(2)
20
18 10-2
10-1
1
10 f (kHz)
102
VP = 14.4 V. (1) THD = 10 %. (2) THD = 0.5 %.
Fig 20. Output power as a function of frequency; 4 load
TDA8595_2
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Product data sheet
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TDA8595
I2C-bus controlled 4 x 45 W power amplifier
55 Po (W)
001aad142
45
(1)
35
(2)
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25 10-2 10-1
1
10 f (kHz)
102
VP = 14.4 V. (1) THD = 10 %. (2) THD = 0.5 %.
Fig 21. Output power as a function of frequency; 2 load
60 Po (W) 40
(1)
001aad143
(2)
20
(3)
0 5 10 15 VP (V) 20
f = 1 kHz. (1) Po(max). (2) THD = 10 %. (3) THD = 0.5 %.
Fig 22. Output power as a function of supply voltage; 4 load
TDA8595_2
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Product data sheet
Rev. 02 -- 21 November 2007
35 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
100 Po (W) 80
(1)
001aad144
60
(2)
40
(3)
20
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0 5 10 15 VP (V) 20
f = 1 kHz. (1) Po(max). (2) THD = 10 %. (3) THD = 0.5 %.
Fig 23. Output power as a function of supply voltage; 2 load
1 THD (%) 10-1
001aad145
10-2
(1) (2)
10-3 10-2
10-1
1
10 f (kHz)
102
VP = 14.4 V; RL = 4 . (1) Po = 1 W. (2) Po = 10 W.
Fig 24. Total harmonic distortion as a function of frequency; normal mode
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
10-1
001aad146
THD (%)
10-2
(1) (2)
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10-3 10-2 10-1
1
10 f (kHz)
102
VP = 14.4 V; RL = 600 . (1) Vo = 1 V. (2) Vo = 5 V.
Fig 25. Total harmonic distortion as a function of frequency; line driver mode
-40 SVRR (dB) -50
001aad147
-60
-70
-80
-90 10-2
10-1
1
10 f (kHz)
102
VP = 14.4 V; RL = 4 ; RS = 1 k; Vripple = 2 V (p-p).
Fig 26. Supply voltage ripple rejection as a function of frequency
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
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NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
100 cs (dB) 90
001aad148
80
70
60
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50 10-2 10-1
1
10 f (kHz)
102
VP = 14.4 V; RL = 4 ; RS = 1 k; Po = 1 W.
Fig 27. Channel separation as a function of frequency
50 P (W) 40
001aad711
30
20
10
0 0 10 20 30 Po (W) 40
VP = 14.4 V; RL = 4 ; f = 1 kHz.
Fig 28. Power dissipation as a function of output power; 4 load
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
38 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
100 P (W) 80
001aad712
60
40
20
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0 0 20 40 60 Po (W) 80
VP = 14.4 V; RL = 2 ; f = 1 kHz.
Fig 29. Power dissipation as a function of output power; 2 load
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
39 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
13. Application information
8.5 V RADSEL (2) 5V
SDA ADSEL
SCL
VP1 21 (20, 21)
VP2 7 (34, 35) 5 (33) DIAG
1 (28) 26 (26) 23 (22)
10 k
STB 2 (29)
STANDBY/ FAST MUTE
I2C-BUS INTERFACE
CLIP DETECT/DIAGNOSTIC
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(4) RS 470 nF
IN1 12 (6)
(1) 1.8 nF
MUTE
10 (4) OUT1+
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
8 (2) OUT1-
(4)
RS
470 nF
IN3 16 (12)
(1) 1.8 nF
MUTE
18 (14) OUT3+
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
20 (17) OUT3-
(4)
RS
470 nF
IN2 13 (7)
(1) 1.8 nF
MUTE
6 (30) OUT2+
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
4 (32) OUT2-
(4)
RS
470 nF
IN4 15 (11)
(1) 1.8 nF
MUTE VP
22 (25) OUT4+
26 dB/ 16 dB
PROTECTION/ DIAGNOSTIC
24 (23) OUT4-
TDA8595J TDA8595SD (TDA8595TH)
27 (36) TAB
11 (5) SVR
(2) 22 F
14 (9) SGND
17 (13) ACGND
(3) (2) 2.2 F
9 (3) PGND1
3 (31) PGND2
19 (16) PGND3
25 (24) PGND4
001aad149
The pin numbers in parenthesis represent TDA8595TH. (1) For EMC reasons a capacitor of 1.8 nF from the input pin to the SGND is advised (optional). (2) The SVR and ACGND capacitors and the RADSEL resistor should first be connected to SGND before connecting to PGND. (3) ACGND capacitor value must be close to 4 x input capacitor value. 4 x 470 nF capacitors can be used as an alternative to the 2.2 F capacitor shown. (4) For EMC reasons, a 10 nF capacitor can be added from each amplifier output to ground.
Fig 30. Test and application information
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
40 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
ACGND 17 (13) TDA8595
1.7 k 0.22 F 1 F
MICROCONTROLLER
100
47 pF
001aad150
The pin number in parenthesis represents TDA8595TH.
Fig 31. Beep input circuit (gain = 0 dB) to apply a microcontroller beep signal to all four amplifiers
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positive output a) negative output
3.9 nF 3.9 nF 47 k 180 pF 47 k
positive output b) negative output
3.9 nF 3.9 nF 180 pF 200
001aad134
Fig 32. Complex loads for measuring THD in line driver mode
8.5 V 5.6 k
4.7 k
18 k
2 STB TDA8595 (29) switch
10 k
3.3 V MICROCONTROLLER
001aad152
The pin number in parenthesis represents TDA8595TH.
Fig 33. Circuit for combined STB and clip detection functions on pin STB
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
41 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
13.1 PCB layout
top
www..com
001aad162
Fig 34. PCB layout of test and application circuit for TDA8595J or TDA8595SD; copper layer top
tob
001aad163
Fig 35. PCB layout of test and application circuit for TDA8595J or TDA8595SD; copper layer bottom (top view)
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
42 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
Sense address select GND VP 2200 F
TDA8594/TDA8595
1 F
top
D8 (00) DA (01)
12C supply Philips Semiconductors + 2.2 F + 470 nF + 2.2 F
+
clip 2
DE (11)
+
10 F
mode on D1
470 nF
diag s. by 12C on GND 10 k Legacy DZ 8.2 V 3 4 Mute off VP -4+ OUT SGND IN 2 1 -3+ +1- OUT +2- SCL GND + 5V SDA
www..com
001aad164
Fig 36. PCB layout of test and application circuit for TDA8595J or TDA8595SD; components top
tob
220 nF 10 k BC859 2 k 10 k 12 k 51 k 250 4.7 k 18 k 22 k 470 nF 470 nF 4 x 470 nF TDA3664 220 nF
001aad165
Fig 37. PCB layout of test and application circuit for TDA8595J or TDA8595SD; components bottom (top view)
14. Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications.
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
43 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
15. Package outline
DBS27P: plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm) SOT827-1
non-concave x Dh
D Eh
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view B: mounting base side
d
A2
B j E A L3 L4
L 1 Z e1 e bp 27 wM Q m c e2 L2 vM
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 19 A2 bp c 0.5 0.3 D(1) d Dh 12 E(1) 15.9 15.5 e 2 e1 1 e2 4 Eh 8 j 3.4 3.1 L 6.8 L2 3.9 3.1 L3 L4 m 4 Q 2.1 1.8 v 0.6 w x Z(1) 1.8 1.2
4.65 0.60 4.35 0.45
29.2 25.8 28.8 25.4
1.15 22.9 0.85 22.1
0.25 0.03
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT827-1 REFERENCES IEC --JEDEC --JEITA --EUROPEAN PROJECTION
ISSUE DATE 03-07-29
Fig 38. Package outline SOT827-1 (DBS27P)
TDA8595_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
44 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
D x
E
A
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y
c E2 HE X v
M
A
D1 D2 1 18
pin 1 index Q E1 A2 (A 3) A4 Lp detail X 36 z e 19 w A
bp
M
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. A2 mm 3.5 A3 A4(1) bp c D (2) D1 D2 1.1 0.9 E (2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 0.65 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.55 2.20 8 0
+0.08 3.5 0.35 -0.04 3.2
0.38 0.32 16.0 13.0 0.25 0.23 15.8 12.6
0.25 0.12 0.03 0.07
Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT851-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-05-04
Fig 39. Package outline SOT851-2 (HSOP36)
TDA8595_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
45 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
RDBS27P: plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads (row spacing 2.54 mm)
SOT878-1
non-concave x D Dh
www..com
Eh
view B: mounting base side d A2
B j E
A L 1 27 c Z e e1 bp w
M
e2
Q L1
v
M
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 13.5 A2 4.65 4.35 bp 0.60 0.45 c 0.5 0.3 D (1) 29.2 28.8 d 25.8 25.4 Dh 12 E (1) 15.9 15.5 e 2 e1 1 e2 2.54 Eh 8 j 3.4 3.1 L 3.75 3.15 L1 3.75 3.15 Q 2.1 1.8 v 0.6 w 0.25 x 0.03 Z (1) 1.8 1.2
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT878-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-01-11 05-01-26
Fig 40. Package outline SOT878-1 (RDBS27P)
TDA8595_2 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
46 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
16. Mounting
2
27
1
1
2.54
26 2
hole diameter min. 0.92
0.08
M
Dimensions in mm
sot878-1_fr
Dimensions in mm. Reflow soldering is the recommended soldering method. www..com Dimension `1' relates to dimension `e1' in Figure 40; dimension `2' relates to dimension `e2' in Figure 40.
Fig 41. SOT878-1 reflow soldering footprint
17. Abbreviations
Table 18. Acronym BCDMOS BTL CMOS DMOS DSP EMC ESR NMOS PMOS POR SOAR SOI Abbreviations Description Bipolar CMOS/DMOS Bridge Tied Load Complementary Metal-Oxide Semiconductor Diffusion Metal Oxide Semiconductor Digital Signal Processor ElectroMagnetic Compatibility Equivalent Series Resistance Negative Metal Oxide Semiconductor Positive Metal Oxide Semiconductor Power-On Reset Safe Operating ARea Silicon On Insulator
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
47 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
18. Revision history
Table 19. Revision history Release date 20071121 Data sheet status Product data sheet Change notice Supersedes TDA8595_1 Document ID TDA8595_2 Modifications:
* * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Changed the term `plop' into `pop'. Figure 1 and Figure 30: changed internal circuit on pin SVR and pull-down transistors on pins STB and DIAG. Figure 33: changed base-emitter resistor value 10 k to 5.6 k. Table 17: changed names of junction temperature-related symbols. Table 17: changed symbol IoM into Ith(o)det(load)AC and adapted parameter description. Section 2.1 and Section 14: added AEC-Q100 quality information. Product data sheet -
www..com
* * * *
TDA8595_1 (9397 750 15067)
20060420
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
48 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
www..com
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TDA8595_2
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 -- 21 November 2007
49 of 50
NXP Semiconductors
TDA8595
I2C-bus controlled 4 x 45 W power amplifier
21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 www..com 7.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Distortion (clip-) detection. . . . . . . . . . . . . . . . . 7 7.4 Output protection and short-circuit operation . . 7 7.5 SOAR protection. . . . . . . . . . . . . . . . . . . . . . . . 7 7.6 Speaker protection . . . . . . . . . . . . . . . . . . . . . . 8 7.7 Standby and mute operation. . . . . . . . . . . . . . . 8 7.7.1 I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.7.2 Legacy mode (pin ADSEL connected to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.8 Start-up and shut-down sequence . . . . . . . . . . 8 7.9 Power-on reset and supply voltage spikes . . . 12 7.10 Engine start and low voltage operation. . . . . . 12 7.11 Overvoltage and load dump protection. . . . . . 15 7.12 Thermal pre-warning and thermal protection . 15 7.13 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.14 Offset detection. . . . . . . . . . . . . . . . . . . . . . . . 17 7.15 DC load detection . . . . . . . . . . . . . . . . . . . . . . 17 7.16 AC load detection . . . . . . . . . . . . . . . . . . . . . . 18 7.17 I2C-bus diagnostic readout . . . . . . . . . . . . . . . 19 2C-bus specification . . . . . . . . . . . . . . . . . . . . 20 8 I 8.1 Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 28 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 28 12 Performance diagrams . . . . . . . . . . . . . . . . . . 33 13 Application information. . . . . . . . . . . . . . . . . . 40 13.1 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 43 14.1 Quality information . . . . . . . . . . . . . . . . . . . . . 43 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44 16 Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 47 18 19 19.1 19.2 19.3 19.4 20 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 49 49 49 49 49 49 50
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 November 2007 Document identifier: TDA8595_2

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